Depending on both the frequencies, FSB : DRAM ratio can yield any one of the 2 operating modes which are Synchronous and Asynchronous. In case of legacy systems where the memory controller was present on the northbridge, while talking about FSB : DRAM ratio we are concerned with the base FSB frequency and the DRAM frequency (base clock rate).This ratio tells us “who is running faster than whom” and when DRAM frequency is more than base FSB or both are the same then we won’t have any issues with system performance. SECTION 3A : FSB:DRAM Ratio on Legacy Systems ![]() Though some say that CL is not that important, but generally it is and its only in the case of bizarre memory access patterns that CL may become less significant. Since data is sequentially placed in memory and a row contains sequential data so its quite simple to catch the fact that columns will be switched more frequently than rows so CAS will have a big impact on performance. t-CL : It is time elapsed between the memory controller sending the address of the column and the data that “first” arrives in response.The 4 important timings with respect to RAM Overclocking are : CAS latency(which is explained below) in nano seconds from clock cycles can be found as follows:ĬAS Latency in ns = CAS delay in cycles x time taken for 1 cycleīut time period is inverse of frequency Hence we get,ĬAS Latency in ns = CAS Latency in cycles x –1ĬAS LAtency in ns = CAS Latency in cycle / Bus Frequency NOTE: All latencies are in terms of clock cycles and actually derived from the current bus speed which is in nanoseconds.For e.g. These timings are specified are in the following order : tCL-tRCD-tRP-tRAS and as you have guessed ‘t’ stands for time. Precharge : Used to activate/deactivate a row in the selected bank before it can be used for read/write operation./CAS : Column access strobe(signal) When this signal goes low, the column in the selected row is ready to be accessed in burst mode of 2, 4 or 8.Now lets get a feel of some of the Signals(strobes) for RAM: ![]() But ironically lowering the timings decreases access time but at the cost of the bandwidth. When it comes to overclocking loosening(increasing) the timings is very effective for increasing the RAM frequency making the modules stable at high frequencies and on the contrary reducing the RAM frequency the timings can be tightened (lowered). The chips used on the DDR ram modules have different types of timings(Primary
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